1. Field of the Invention
The present invention relates, in general, to semiconductor packaging, and more particularly, to a method of molding a ball grid array semiconductor package that prevents the accumulation of an electrostatic charge in the package during molding, thereby preventing damage to the components in the package caused by an electrostatic discharge.
2. Description of the Related Art
The recent trend in consumer electronics has been toward smaller, lighter products having improved capabilities and capacities, which has, in turn, resulted in a demand for semiconductor chips that are smaller, more highly integrated, and of higher capacity. Accordingly, modern semiconductor packages must have excellent electrical characteristics, high heat dissipating capabilities, and a large input/output-terminal capacity, to enable such small, highly integrated, and efficient semiconductor chips to perform as expected.
Ball grid array (BGA) semiconductor packages have been proposed and widely used as an exemplary package capable of enabling small, efficient and highly integrated semiconductor chips to meet their design goals effectively. BGA packages are easily formed on a conventional printed circuit board (PCB) and can effectively reduce the overall length of electric circuits incorporating them. BGA packages also utilize power- and/or ground-bonding areas more effectively, thus yielding excellent electric characteristics. Also, the input/output terminal density of BGA packages is greater than that of conventional quad flat packages (QFPs), which better comports with the trend toward smaller, denser packages.
FIGS. 10a and 10b are top and bottom plan views, respectively, of a conventional, strip-type multiple-package PCB 10 typically used in the manufacture of BGA semiconductor packages. FIG. 15 is an enlarged plan view showing the area around a mold runner gate located in the upper left hand corner of each individual PCB of the multiple PCB 10 of FIG. 10a. The following description of the construction of the conventional PCB is with reference to FIGS. 10a, 10b and 15.
As shown in the drawings, the typical PCB 10 comprises a dielectric substrate 11 made of a thermosetting resin, e.g., a bismaleimidetriazine or polyimide resin. A plurality of conductive traces 12 are formed on each side of the substrate to form a predetermined circuit pattern on each side thereof. A plurality of die, or chip, mounting plates 16 are centrally provided on the top surface of the substrate 11 for the mounting of semiconductor chips thereon. A plurality of conductive via holes 13 are formed through the substrate 11 to electrically connect the conductive traces 12 of both sides of the PCB to each other. A plurality of solder ball lands 14 are electrically connected to the conductive traces 12 on the bottom surface of the substrate 11.
A non-conductive solder mask 15 coats both sides of the substrate 11, except for selected areas of the conductive traces 12, e.g., around the edge of the chip mounting plate 16, and on the solder ball lands 14, and serves to electrically isolate the traces 12 from each other and to protect them from harmful environmental elements.
As shown in FIGS. 10a and 15, a mold runner gate 17, comprising a thin, conductive metal plate or plating of, e.g., gold or palladium, extends from a corner of the substrate 11 to the chip mounting plate 16, and serves to guide melted molding compound, e.g., a resin, into the region of the chip mounting plate 16 during a package molding operation described in more detail below. The bonding strength between the material of the mold gate runner 17 and the molding resin is much lower than that between the resin and the solder mask 15, which enables the resin to be easily de-gated from the gate 17 without damaging the conductive traces 12 after molding is complete.
The mold runner gate 17 is electrically connected to a ground ring 25 formed along the edge of the chip mounting plate 16 through a conductive ground trace 21. The grounded elements of a semiconductor chip (not shown in FIG. 10a) are electrically connected to the ground ring 25 by means of bonding wires (not shown) that extend between the chip and the ground ring. In the BGA package, ground signals applied from the semiconductor chip to the mold runner gate 17 enable precise measurement of voltage drops occurring between the chip and ground. Likewise, any voltage drops occurring in the wire bonds between the chip and the conductive traces 12 can also be checked easily and precisely. The grounded mold runner gate/ground ring arrangement therefore forms an effective common ground area for purposes of complete circuit definition within the BGA package.
As seen in FIGS. 10a and 10b, tooling holes 18 are used in the strip-shaped PCB 10 to position and fix the PCB in a molding tool assembly. Singularizing holes 19 are used as reference points during singularization, or separation, of the individual BGA packages from the multiple-package PCB, which is typically accomplished by die cutting. The dotted square 19' defined by the singularizing holes 19 corresponds to the line along which the substrate is cut when the individual BGA packages are separated from the plurality of packages simultaneously fabricated on the PCB 10.
FIG. 16 is a sectional view of the PCB 10 taken along the line IV--IV in FIG. 15. As may be seen in FIG. 16, the solder mask 15 is thicker than the mold runner gate 17, and has an opening through it to expose a portion of the upper surface of the mold runner gate. The solder mask 15 is also locally relieved to expose areas on the solder ball lands 14 formed on the conductive traces 12 on the bottom surface of the PCB 10 so that solder balls (not shown) can be attached thereto.
FIG. 11 is a sectional view through the region around a via hole 13 of the PCB 10. As shown in the drawing, the via holes 13 are formed on respective conductive traces 12. The interior wall of the via hole 13 is plated with a conductive metal, while the solder mask 15 overlays the top surface of the trace 12 and fills the void in the via hole 13. A solder ball 80 is welded to the solder ball land 14 and is used as an input/output terminal of the package.
FIG. 12 is a sectional view through a tooling hole 18, as taken along the line III--III in FIG. 10b. FIG. 12 reveals that the tooling hole 18 is, like the via hole 13, formed through the thickness of the substrate 11 of the PCB. However, unlike the via hole 13, the tooling hole 18 does not include a conductive layer on its interior surface that electrically connects the upper and lower surfaces of the board, nor does the solder mask 15 fill the interior void of the hole.
A conventional BGA semiconductor package 1 that incorporates a conventional PCB 10 of the type described above is shown in elevational cross-section in FIG. 18. Typically, a plurality of such packages are simultaneously fabricated on the PCB 10 in the following manner. First, a plurality of semiconductor chips 40 are mounted, typically by means of a bonding layer (not shown), on the strip-shaped PCB 10, one on each of the chip mounting plates 16. Each chip 40 is then electrically connected to areas on the conductive traces 12 which are free of the solder mask 15 using a plurality of fine bonding wires 50.
After wire bonding is complete, a plurality of resin envelopes 70 are molded onto the upper surface of the PCB 10 around each of the chips 40 and its associated bonding wires 50 to encapsulate and protect them against damaging mechanical and electrical environmental elements. After molding, a plurality of solder balls 80, which are used as the input and output terminals of the packages 1, are respectively welded to the solder ball lands 14. The solder ball welding step is followed by a singularizing step in which the simultaneously formed plurality of BGA packages 1 are each separated from the PCB 10, typically by die cutting, into individual BGA packages 1 of the type illustrated in FIG. 18.
In the above manufacturing process, the molding step is carried out with the individual semiconductor chips 40 mounted on the PCB 10 and positioned between top and bottom molds 30a and 30b, as shown in FIG. 14. The encapsulating resin reinforces the delicate wires 50 and bonds them securely to both the associated chip 40 and the conductive traces 12. FIG. 13a is a partially broken-away bottom perspective view of a typical top mold 30a used in the molding step of FIG. 14. FIG. 13b is an enlarged view of the region labeled "C" in FIG. 13a.
As seen in FIG. 14, the bottom mold 30b has an upper depression 31' in its top surface, which serves to seat the PCB 10 therein, while the top mold 30a is provided with a plurality of lower depressions 31 (see FIG. 13a), each having a configuration corresponding to the top portion of the molded envelope 70 of each BGA package 1. A plurality of cavities 34 (FIG. 14) is thus defined between the lower depressions 31 of the top mold 30a and the top surface of the PCB 10, each of which encloses one of the semiconductor chips 40 and its associated bonding wires 50 positioned on the top surface of the PCB 10.
As seen in FIGS. 13a and 13b, a runner 32 is formed in the top mold 30a at a position near the corner of each cavity to guide injected molten molding resin (not shown) into the cavity 34. The runners 32 are formed at positions corresponding to the positions of the respective mold runner gates 17 (see FIGS. 10a, 17) on the PCB 10. The lower surface of the top mold 30a mates with the upper surface of the bottom mold 30b on opposite sides of the runner 32 to define a conduit for the introduction of the resin into the cavity 34.
The molding resin is injected under pressure into the cavity 34 through the runner 32, thereby forming a resin envelope 70 on the upper surface of the PCB 10 which completely encapsulates the chip and its associated bonding wires 50. The top mold 30a is provided with a plurality of tooling pins 33 that extend through the tooling holes 18 of the PCB 10 and into corresponding apertures (not shown) in the bottom mold 30b, thus accurately locating and securely fixing the PCB 10 within the molds during the molding process. In this regard, it should be noted that the mounting of the tooling pins 33 is not limited to the upper mold 30a; thus, in an alternative configuration, the tooling pins can as easily be mounted on the bottom mold 30b to extend upwardly through the tooling holes 18 in the PCB 10.
FIG. 17 is an enlarged, partial sectional view showing the PCB 10 of FIG. 16 compressed between the top and bottom molds during the typical package molding process. Importantly, it may be seen from FIG. 17 that both the mold runner gate 17 and the solder ball lands 14 on the PCB 10 are separated from the top and bottom molds 30a, 30b, respectively, by the thickness of the dielectric solder mask 15, i.e., that they are electrically isolated from both the top and bottom molds 30a, 30b, respectively, during the molding process.
During molding, hot molten molding resin under high pressure is injected into the cavity 34 through the conduit formed between the runner 32 in the top mold 30a and the mold runner gate 17 on the PCB 10, causing the molten resin to flow over the chip 40, the conductive bonding wires 50, and the surface of the PCB 10 with frictional contact. This frictional flow of the molten resin over these components generates static electricity, which is induced on the chip 40, the wires 50 and the traces 12 of the PCB 10, thereby causing an undesirable accumulation of a strong electrostatic charge on these elements.
In those cases where the supply voltage specified for the semiconductor chips, or the allowable variation therein, is relatively high, a rapid electrostatic discharge of the above charge accumulation to ground will not necessarily result in any damage to the components of the BGA package. However, when the level of supply voltage specified for the semiconductor chips or allowable variation therein is relatively low, then a rapid discharge of the accumulated charge can cause permanent damage to the semiconductor chip 40, the bonding wires 50 and/or the conductive traces 12 of the BGA packages.
This undesirable discharge can occur when the packages are removed from the molds after the molding process, or when they are brought into contact with other processing equipment during manufacture. When this discharge occurs, components in the semiconductor chip, the bonding wires, and/or the fine circuit patterns of the PCB itself may be irreparably burnt open. Therefore, the accumulation of an electrostatic charge on the components of a BGA package during molding presents a potentially serious problem that must be overcome if BGA packages are to remain a viable semiconductor packaging candidate, especially in view of the recent trend toward chips that are smaller, higher capacity, and more highly integrated.